FIG. 6 is an electric circuit diagram showing a typical direct-current stabilization power supply device 1 of a conventional art. The direct-current stabilization power supply device 1 is constituted by a PNP bipolar transistor, etc., and is a three-terminal regulator that has a two-chip structure including a control IC 2 and a power transistor tr being connected in series between an input terminal p1 and an output terminal p2, so as to be used for a relatively large current such as 3 to 10 [A]. The control IC 2 is provided with a constant voltage circuit 3, an overcurrent protective circuit 4, and a short-circuit protective circuit 5.
An output voltage vo to the output terminal p2 is applied to an inverted input terminal of an error amplifier 6 of the constant voltage circuit 3 via partial pressure resistances r1 and r2. And a non-inverted input terminal of the error amplifier 6 receives a base voltage vref of a reference voltage source 7. The smaller a partial pressure value vadj of the output voltage vo is as compared with the reference voltage vref, the error amplifier 6 derives a larger control current. The control current is applied to NPN transistors q1 and q2 that make a Darlington connection for controlling a base current id of the power transistor tr. Therefore, the smaller the output voltage vo is, the larger base current id becomes so as to realize a constant voltage operation for maintaining the output voltage vo at a certain level. The emitter of the transistor q2 is connected with a ground terminal p3 via a transistor q3 and a base resistance rs that make a diode connection.
The base resistance rs is connected with a power source line 8 of an input voltage vi via a transistor q4 and a constant current circuit f1 beside the overcurrent protective circuit 4. The transistor q4 and a transistor q5 constitute a current mirror circuit. The collector of the transistor q4 is connected with the output of the error amplifier 6, namely, the base of the transistor q1. In the overcurrent protective circuit 4, between the power source line 8 of the input voltage vi and a power source line 9 of a ground potential, a serial circuit having a constant current circuit f2 and a transistor q6 is connected. Further, between the power source lines 8 and 9, a serial circuit having a transistor q7 and partial resistances r3 and r4 is connected. The reference voltage vref is applied to the base of the PNP transistor q6 and is applied to partial pressure resistances r3 and r4 at the NPN transistor q7 whose base is connected with the emitter of the transistor q6. A connecting point pll between the partial pressure resistances r3 and r4 is connected with the emitter of the transistor q5. Here, when the power transistor tr has a current amplification factor of hfe, an output current io of the power transistor tr is represented by: EQU io=id.times.hfe (1).
Meanwhile, a voltage vbe between the base and emitter of a transistor is represented by: EQU vbe=k.multidot.T/q.multidot.ln(ic/is) (2).
Here, k stands for a Boltzmann constant, q stands for a charge amount, T stands for an absolute temperature, is stands for a reverse saturation current, and ic stands for a collector current.
Therefore, for example, when the transistor q4 and q5 have an emitter area ratio of 1:1, EQU vref.times.r4/(f3+r4)=id.times.rs (3)
is established. Namely, when the base current id satisfies the equation(3), the transistor q5 is brought into conduction, a control current is bypassed from the error amplifier 6, and the base current id is reduced, so as to perform an overcurrent protecting operation.
When the overcurrent protecting operation is carried out as described above so as to reduce the base current id and the output voltage vo, the short-circuit protective circuit 5 further reduces the base current id as follows: in the short-circuit protective circuit 5, a PNP transistor q8 is connected between the base of the transistor q1 and the power source line 9 which is at a ground level, and the transistor qB is controlled by an NPN transistor q9. The collector of the transistor q9 is connected with the base of the transistor q8, and the partial pressure value vadj of the output voltage vo is applied from the partial resistances r1 and r2 to the emitter of the transistor q9. The base of the transistor q9 is connected with a connecting point between the transistors q2 and q3. Moreover, between (a)a connecting point of the emitter of the transistor q1 and the base of the transistor q2 and (b) the base of the transistor q9, a resistance r5 is connected, and a resistance r6 is connected in parallel with the transistor q3.
Hence, when the partial pressure value vadj is reduced due to an output short circuit, etc., and the transistor q9 is conducting, the transistor q8 is brought into conduction and a control current applied to the transistor q1 is bypassed, so as to perform a short-circuit protective operation. Thus, in this case, a base current ids and a short-circuit current ios are determined by the following equations. EQU ids=vbe(q9)/r6 (4) EQU ios=ids.times.hfe (5)
With this arrangement, as shown in FIG. 7, it is possible to achieve a so-called fold-back characteristic between the output current vo and the output current io.
In the case of the direct-current stabilization power supply device 1 having the above-mentioned construction, when the power transistor tr has, for example, a current amplification factor hfe(min) of 65 under saturation, the base current id needs to be at least 120[mA] in order to achieve the output current io=7.5[A]. In view of a current reduction caused by irregularity of the process, it is necessary to set the base current id at, for example, 180 [mA]. Meanwhile, when the power transistor tr is not saturated, in the case of the current amplification factor hfe(max)=150, the maximum value of the output current io(max) is determined by the following equation. EQU io(max)=180[mA].times.150=27[A] (6)
Thus, an output current which is about 3.6 times as large as a rating current of 7.5[A] may be applied. For instance, in the case of the input voltage vi=7[V] and the output voltage vo=3[V], the power transistor tr is supplied with power of: EQU P=(vi-vo).times.io(max)=(7-3).times.27=108[W] (7).
Further, in the case of a short circuit, larger power is applied, so that it is necessary to form an emitter area of the power transistor tr that is sufficiently larger than a rating value, resulting in a costly chip of the power transistor tr. Furthermore, in a load-side circuit, a current suppressing operation is not performed until the maximum current io(max), so that the load-side circuit needs to have a construction which responds to an excessive current. Moreover, in the direct-current stabilization power supply device 1 having the above-mentioned construction, the minimum operating voltage vi(min) is determined by the following equation. EQU vi(min)=id.times.rs+vbe(q3)+vbe(q2)+vbe(q1)+vce (8)
The problem is that the minimum operating voltage vi (min) is high. Here, vce represents a voltage between the collector and emitter of a PNP transistor which is located between the power source line 8 and the output terminal of the input voltage vi.